wok diff libdrm/stuff/libdrm-2.4.21-b803918f3f.patch @ rev 18621
Up tazpanel (552)
| author | Pascal Bellard <pascal.bellard@slitaz.org> |
|---|---|
| date | Sat Nov 21 21:53:12 2015 +0100 (2015-11-21) |
| parents | |
| children |
line diff
1.1 --- /dev/null Thu Jan 01 00:00:00 1970 +0000 1.2 +++ b/libdrm/stuff/libdrm-2.4.21-b803918f3f.patch Sat Nov 21 21:53:12 2015 +0100 1.3 @@ -0,0 +1,506 @@ 1.4 +diff --git a/intel/intel_bufmgr_gem.c b/intel/intel_bufmgr_gem.c 1.5 +index a8e072d..3446390 100644 1.6 +--- a/intel/intel_bufmgr_gem.c 1.7 ++++ b/intel/intel_bufmgr_gem.c 1.8 +@@ -93,6 +93,7 @@ typedef struct _drm_intel_bufmgr_gem { 1.9 + /** Array of lists of cached gem objects of power-of-two sizes */ 1.10 + struct drm_intel_gem_bo_bucket cache_bucket[14 * 4]; 1.11 + int num_buckets; 1.12 ++ time_t time; 1.13 + 1.14 + uint64_t gtt_size; 1.15 + int available_fences; 1.16 +@@ -132,6 +133,7 @@ struct _drm_intel_bo_gem { 1.17 + */ 1.18 + uint32_t tiling_mode; 1.19 + uint32_t swizzle_mode; 1.20 ++ unsigned long stride; 1.21 + 1.22 + time_t free_time; 1.23 + 1.24 +@@ -200,8 +202,9 @@ drm_intel_gem_bo_get_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 1.25 + uint32_t * swizzle_mode); 1.26 + 1.27 + static int 1.28 +-drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 1.29 +- uint32_t stride); 1.30 ++drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, 1.31 ++ uint32_t tiling_mode, 1.32 ++ uint32_t stride); 1.33 + 1.34 + static void drm_intel_gem_bo_unreference_locked_timed(drm_intel_bo *bo, 1.35 + time_t time); 1.36 +@@ -251,7 +254,7 @@ drm_intel_gem_bo_tile_size(drm_intel_bufmgr_gem *bufmgr_gem, unsigned long size, 1.37 + */ 1.38 + static unsigned long 1.39 + drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, 1.40 +- unsigned long pitch, uint32_t tiling_mode) 1.41 ++ unsigned long pitch, uint32_t *tiling_mode) 1.42 + { 1.43 + unsigned long tile_width; 1.44 + unsigned long i; 1.45 +@@ -259,10 +262,10 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, 1.46 + /* If untiled, then just align it so that we can do rendering 1.47 + * to it with the 3D engine. 1.48 + */ 1.49 +- if (tiling_mode == I915_TILING_NONE) 1.50 ++ if (*tiling_mode == I915_TILING_NONE) 1.51 + return ALIGN(pitch, 64); 1.52 + 1.53 +- if (tiling_mode == I915_TILING_X) 1.54 ++ if (*tiling_mode == I915_TILING_X) 1.55 + tile_width = 512; 1.56 + else 1.57 + tile_width = 128; 1.58 +@@ -271,6 +274,14 @@ drm_intel_gem_bo_tile_pitch(drm_intel_bufmgr_gem *bufmgr_gem, 1.59 + if (bufmgr_gem->gen >= 4) 1.60 + return ROUND_UP_TO(pitch, tile_width); 1.61 + 1.62 ++ /* The older hardware has a maximum pitch of 8192 with tiled 1.63 ++ * surfaces, so fallback to untiled if it's too large. 1.64 ++ */ 1.65 ++ if (pitch > 8192) { 1.66 ++ *tiling_mode = I915_TILING_NONE; 1.67 ++ return ALIGN(pitch, 64); 1.68 ++ } 1.69 ++ 1.70 + /* Pre-965 needs power of two tile width */ 1.71 + for (i = tile_width; i < pitch; i <<= 1) 1.72 + ; 1.73 +@@ -549,7 +560,9 @@ static drm_intel_bo * 1.74 + drm_intel_gem_bo_alloc_internal(drm_intel_bufmgr *bufmgr, 1.75 + const char *name, 1.76 + unsigned long size, 1.77 +- unsigned long flags) 1.78 ++ unsigned long flags, 1.79 ++ uint32_t tiling_mode, 1.80 ++ unsigned long stride) 1.81 + { 1.82 + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bufmgr; 1.83 + drm_intel_bo_gem *bo_gem; 1.84 +@@ -615,6 +628,13 @@ retry: 1.85 + bucket); 1.86 + goto retry; 1.87 + } 1.88 ++ 1.89 ++ if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, 1.90 ++ tiling_mode, 1.91 ++ stride)) { 1.92 ++ drm_intel_gem_bo_free(&bo_gem->bo); 1.93 ++ goto retry; 1.94 ++ } 1.95 + } 1.96 + } 1.97 + pthread_mutex_unlock(&bufmgr_gem->lock); 1.98 +@@ -642,6 +662,17 @@ retry: 1.99 + return NULL; 1.100 + } 1.101 + bo_gem->bo.bufmgr = bufmgr; 1.102 ++ 1.103 ++ bo_gem->tiling_mode = I915_TILING_NONE; 1.104 ++ bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 1.105 ++ bo_gem->stride = 0; 1.106 ++ 1.107 ++ if (drm_intel_gem_bo_set_tiling_internal(&bo_gem->bo, 1.108 ++ tiling_mode, 1.109 ++ stride)) { 1.110 ++ drm_intel_gem_bo_free(&bo_gem->bo); 1.111 ++ return NULL; 1.112 ++ } 1.113 + } 1.114 + 1.115 + bo_gem->name = name; 1.116 +@@ -650,8 +681,6 @@ retry: 1.117 + bo_gem->reloc_tree_fences = 0; 1.118 + bo_gem->used_as_reloc_target = 0; 1.119 + bo_gem->has_error = 0; 1.120 +- bo_gem->tiling_mode = I915_TILING_NONE; 1.121 +- bo_gem->swizzle_mode = I915_BIT_6_SWIZZLE_NONE; 1.122 + bo_gem->reusable = 1; 1.123 + 1.124 + drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); 1.125 +@@ -669,7 +698,8 @@ drm_intel_gem_bo_alloc_for_render(drm_intel_bufmgr *bufmgr, 1.126 + unsigned int alignment) 1.127 + { 1.128 + return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 1.129 +- BO_ALLOC_FOR_RENDER); 1.130 ++ BO_ALLOC_FOR_RENDER, 1.131 ++ I915_TILING_NONE, 0); 1.132 + } 1.133 + 1.134 + static drm_intel_bo * 1.135 +@@ -678,7 +708,8 @@ drm_intel_gem_bo_alloc(drm_intel_bufmgr *bufmgr, 1.136 + unsigned long size, 1.137 + unsigned int alignment) 1.138 + { 1.139 +- return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0); 1.140 ++ return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, 0, 1.141 ++ I915_TILING_NONE, 0); 1.142 + } 1.143 + 1.144 + static drm_intel_bo * 1.145 +@@ -687,10 +718,8 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, 1.146 + unsigned long *pitch, unsigned long flags) 1.147 + { 1.148 + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *)bufmgr; 1.149 +- drm_intel_bo *bo; 1.150 + unsigned long size, stride; 1.151 + uint32_t tiling; 1.152 +- int ret; 1.153 + 1.154 + do { 1.155 + unsigned long aligned_y; 1.156 +@@ -717,24 +746,17 @@ drm_intel_gem_bo_alloc_tiled(drm_intel_bufmgr *bufmgr, const char *name, 1.157 + aligned_y = ALIGN(y, 32); 1.158 + 1.159 + stride = x * cpp; 1.160 +- stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling); 1.161 ++ stride = drm_intel_gem_bo_tile_pitch(bufmgr_gem, stride, tiling_mode); 1.162 + size = stride * aligned_y; 1.163 + size = drm_intel_gem_bo_tile_size(bufmgr_gem, size, tiling_mode); 1.164 + } while (*tiling_mode != tiling); 1.165 +- 1.166 +- bo = drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags); 1.167 +- if (!bo) 1.168 +- return NULL; 1.169 +- 1.170 +- ret = drm_intel_gem_bo_set_tiling(bo, tiling_mode, stride); 1.171 +- if (ret != 0) { 1.172 +- drm_intel_gem_bo_unreference(bo); 1.173 +- return NULL; 1.174 +- } 1.175 +- 1.176 + *pitch = stride; 1.177 + 1.178 +- return bo; 1.179 ++ if (tiling == I915_TILING_NONE) 1.180 ++ stride = 0; 1.181 ++ 1.182 ++ return drm_intel_gem_bo_alloc_internal(bufmgr, name, size, flags, 1.183 ++ tiling, stride); 1.184 + } 1.185 + 1.186 + /** 1.187 +@@ -791,6 +813,7 @@ drm_intel_bo_gem_create_from_name(drm_intel_bufmgr *bufmgr, 1.188 + } 1.189 + bo_gem->tiling_mode = get_tiling.tiling_mode; 1.190 + bo_gem->swizzle_mode = get_tiling.swizzle_mode; 1.191 ++ /* XXX stride is unknown */ 1.192 + drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); 1.193 + 1.194 + DBG("bo_create_from_handle: %d (%s)\n", handle, bo_gem->name); 1.195 +@@ -829,6 +852,9 @@ drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time) 1.196 + { 1.197 + int i; 1.198 + 1.199 ++ if (bufmgr_gem->time == time) 1.200 ++ return; 1.201 ++ 1.202 + for (i = 0; i < bufmgr_gem->num_buckets; i++) { 1.203 + struct drm_intel_gem_bo_bucket *bucket = 1.204 + &bufmgr_gem->cache_bucket[i]; 1.205 +@@ -846,6 +872,8 @@ drm_intel_gem_cleanup_bo_cache(drm_intel_bufmgr_gem *bufmgr_gem, time_t time) 1.206 + drm_intel_gem_bo_free(&bo_gem->bo); 1.207 + } 1.208 + } 1.209 ++ 1.210 ++ bufmgr_gem->time = time; 1.211 + } 1.212 + 1.213 + static void 1.214 +@@ -854,7 +882,6 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) 1.215 + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1.216 + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1.217 + struct drm_intel_gem_bo_bucket *bucket; 1.218 +- uint32_t tiling_mode; 1.219 + int i; 1.220 + 1.221 + /* Unreference all the target buffers */ 1.222 +@@ -883,9 +910,7 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) 1.223 + 1.224 + bucket = drm_intel_gem_bo_bucket_for_size(bufmgr_gem, bo->size); 1.225 + /* Put the buffer into our internal cache for reuse if we can. */ 1.226 +- tiling_mode = I915_TILING_NONE; 1.227 + if (bufmgr_gem->bo_reuse && bo_gem->reusable && bucket != NULL && 1.228 +- drm_intel_gem_bo_set_tiling(bo, &tiling_mode, 0) == 0 && 1.229 + drm_intel_gem_bo_madvise_internal(bufmgr_gem, bo_gem, 1.230 + I915_MADV_DONTNEED)) { 1.231 + bo_gem->free_time = time; 1.232 +@@ -894,8 +919,6 @@ drm_intel_gem_bo_unreference_final(drm_intel_bo *bo, time_t time) 1.233 + bo_gem->validate_index = -1; 1.234 + 1.235 + DRMLISTADDTAIL(&bo_gem->head, &bucket->head); 1.236 +- 1.237 +- drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time); 1.238 + } else { 1.239 + drm_intel_gem_bo_free(bo); 1.240 + } 1.241 +@@ -925,6 +948,7 @@ static void drm_intel_gem_bo_unreference(drm_intel_bo *bo) 1.242 + 1.243 + pthread_mutex_lock(&bufmgr_gem->lock); 1.244 + drm_intel_gem_bo_unreference_final(bo, time.tv_sec); 1.245 ++ drm_intel_gem_cleanup_bo_cache(bufmgr_gem, time.tv_sec); 1.246 + pthread_mutex_unlock(&bufmgr_gem->lock); 1.247 + } 1.248 + } 1.249 +@@ -982,12 +1006,9 @@ static int drm_intel_gem_bo_map(drm_intel_bo *bo, int write_enable) 1.250 + &set_domain); 1.251 + } while (ret == -1 && errno == EINTR); 1.252 + if (ret != 0) { 1.253 +- ret = -errno; 1.254 + fprintf(stderr, "%s:%d: Error setting to CPU domain %d: %s\n", 1.255 + __FILE__, __LINE__, bo_gem->gem_handle, 1.256 + strerror(errno)); 1.257 +- pthread_mutex_unlock(&bufmgr_gem->lock); 1.258 +- return ret; 1.259 + } 1.260 + 1.261 + pthread_mutex_unlock(&bufmgr_gem->lock); 1.262 +@@ -1062,9 +1083,7 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) 1.263 + DRM_IOCTL_I915_GEM_SET_DOMAIN, 1.264 + &set_domain); 1.265 + } while (ret == -1 && errno == EINTR); 1.266 +- 1.267 + if (ret != 0) { 1.268 +- ret = -errno; 1.269 + fprintf(stderr, "%s:%d: Error setting domain %d: %s\n", 1.270 + __FILE__, __LINE__, bo_gem->gem_handle, 1.271 + strerror(errno)); 1.272 +@@ -1072,7 +1091,7 @@ int drm_intel_gem_bo_map_gtt(drm_intel_bo *bo) 1.273 + 1.274 + pthread_mutex_unlock(&bufmgr_gem->lock); 1.275 + 1.276 +- return ret; 1.277 ++ return 0; 1.278 + } 1.279 + 1.280 + int drm_intel_gem_bo_unmap_gtt(drm_intel_bo *bo) 1.281 +@@ -1587,7 +1606,7 @@ drm_intel_gem_bo_mrb_exec2(drm_intel_bo *bo, int used, 1.282 + 1.283 + if (ret != 0) { 1.284 + ret = -errno; 1.285 +- if (ret == -ENOMEM) { 1.286 ++ if (ret == -ENOSPC) { 1.287 + fprintf(stderr, 1.288 + "Execbuffer fails to pin. " 1.289 + "Estimate: %u. Actual: %u. Available: %u\n", 1.290 +@@ -1671,34 +1690,56 @@ drm_intel_gem_bo_unpin(drm_intel_bo *bo) 1.291 + } 1.292 + 1.293 + static int 1.294 +-drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 1.295 +- uint32_t stride) 1.296 ++drm_intel_gem_bo_set_tiling_internal(drm_intel_bo *bo, 1.297 ++ uint32_t tiling_mode, 1.298 ++ uint32_t stride) 1.299 + { 1.300 + drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1.301 + drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1.302 + struct drm_i915_gem_set_tiling set_tiling; 1.303 + int ret; 1.304 + 1.305 +- if (bo_gem->global_name == 0 && *tiling_mode == bo_gem->tiling_mode) 1.306 ++ if (bo_gem->global_name == 0 && 1.307 ++ tiling_mode == bo_gem->tiling_mode && 1.308 ++ stride == bo_gem->stride) 1.309 + return 0; 1.310 + 1.311 + memset(&set_tiling, 0, sizeof(set_tiling)); 1.312 +- set_tiling.handle = bo_gem->gem_handle; 1.313 +- 1.314 + do { 1.315 +- set_tiling.tiling_mode = *tiling_mode; 1.316 ++ set_tiling.handle = bo_gem->gem_handle; 1.317 ++ set_tiling.tiling_mode = tiling_mode; 1.318 + set_tiling.stride = stride; 1.319 + 1.320 + ret = ioctl(bufmgr_gem->fd, 1.321 + DRM_IOCTL_I915_GEM_SET_TILING, 1.322 + &set_tiling); 1.323 + } while (ret == -1 && errno == EINTR); 1.324 +- if (ret == 0) { 1.325 +- bo_gem->tiling_mode = set_tiling.tiling_mode; 1.326 +- bo_gem->swizzle_mode = set_tiling.swizzle_mode; 1.327 ++ if (ret == -1) 1.328 ++ return -errno; 1.329 ++ 1.330 ++ bo_gem->tiling_mode = set_tiling.tiling_mode; 1.331 ++ bo_gem->swizzle_mode = set_tiling.swizzle_mode; 1.332 ++ bo_gem->stride = set_tiling.stride; 1.333 ++ return 0; 1.334 ++} 1.335 ++ 1.336 ++static int 1.337 ++drm_intel_gem_bo_set_tiling(drm_intel_bo *bo, uint32_t * tiling_mode, 1.338 ++ uint32_t stride) 1.339 ++{ 1.340 ++ drm_intel_bufmgr_gem *bufmgr_gem = (drm_intel_bufmgr_gem *) bo->bufmgr; 1.341 ++ drm_intel_bo_gem *bo_gem = (drm_intel_bo_gem *) bo; 1.342 ++ int ret; 1.343 ++ 1.344 ++ /* Linear buffers have no stride. By ensuring that we only ever use 1.345 ++ * stride 0 with linear buffers, we simplify our code. 1.346 ++ */ 1.347 ++ if (*tiling_mode == I915_TILING_NONE) 1.348 ++ stride = 0; 1.349 ++ 1.350 ++ ret = drm_intel_gem_bo_set_tiling_internal(bo, *tiling_mode, stride); 1.351 ++ if (ret == 0) 1.352 + drm_intel_bo_gem_set_in_aperture_size(bufmgr_gem, bo_gem); 1.353 +- } else 1.354 +- ret = -errno; 1.355 + 1.356 + *tiling_mode = bo_gem->tiling_mode; 1.357 + return ret; 1.358 +diff --git a/xf86drmMode.c b/xf86drmMode.c 1.359 +index f330e6f..ecb1fd5 100644 1.360 +--- a/xf86drmMode.c 1.361 ++++ b/xf86drmMode.c 1.362 +@@ -52,6 +52,12 @@ 1.363 + #define U642VOID(x) ((void *)(unsigned long)(x)) 1.364 + #define VOID2U64(x) ((uint64_t)(unsigned long)(x)) 1.365 + 1.366 ++static inline DRM_IOCTL(int fd, int cmd, void *arg) 1.367 ++{ 1.368 ++ int ret = drmIoctl(fd, cmd, arg); 1.369 ++ return ret < 0 ? -errno : ret; 1.370 ++} 1.371 ++ 1.372 + /* 1.373 + * Util functions 1.374 + */ 1.375 +@@ -242,7 +248,7 @@ int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth, 1.376 + f.depth = depth; 1.377 + f.handle = bo_handle; 1.378 + 1.379 +- if ((ret = drmIoctl(fd, DRM_IOCTL_MODE_ADDFB, &f))) 1.380 ++ if ((ret = DRM_IOCTL(fd, DRM_IOCTL_MODE_ADDFB, &f))) 1.381 + return ret; 1.382 + 1.383 + *buf_id = f.fb_id; 1.384 +@@ -251,7 +257,7 @@ int drmModeAddFB(int fd, uint32_t width, uint32_t height, uint8_t depth, 1.385 + 1.386 + int drmModeRmFB(int fd, uint32_t bufferId) 1.387 + { 1.388 +- return drmIoctl(fd, DRM_IOCTL_MODE_RMFB, &bufferId); 1.389 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_RMFB, &bufferId); 1.390 + 1.391 + 1.392 + } 1.393 +@@ -289,7 +295,7 @@ int drmModeDirtyFB(int fd, uint32_t bufferId, 1.394 + dirty.clips_ptr = VOID2U64(clips); 1.395 + dirty.num_clips = num_clips; 1.396 + 1.397 +- return drmIoctl(fd, DRM_IOCTL_MODE_DIRTYFB, &dirty); 1.398 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_DIRTYFB, &dirty); 1.399 + } 1.400 + 1.401 + 1.402 +@@ -344,7 +350,7 @@ int drmModeSetCrtc(int fd, uint32_t crtcId, uint32_t bufferId, 1.403 + } else 1.404 + crtc.mode_valid = 0; 1.405 + 1.406 +- return drmIoctl(fd, DRM_IOCTL_MODE_SETCRTC, &crtc); 1.407 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETCRTC, &crtc); 1.408 + } 1.409 + 1.410 + /* 1.411 +@@ -361,7 +367,7 @@ int drmModeSetCursor(int fd, uint32_t crtcId, uint32_t bo_handle, uint32_t width 1.412 + arg.height = height; 1.413 + arg.handle = bo_handle; 1.414 + 1.415 +- return drmIoctl(fd, DRM_IOCTL_MODE_CURSOR, &arg); 1.416 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR, &arg); 1.417 + } 1.418 + 1.419 + int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y) 1.420 +@@ -373,7 +379,7 @@ int drmModeMoveCursor(int fd, uint32_t crtcId, int x, int y) 1.421 + arg.x = x; 1.422 + arg.y = y; 1.423 + 1.424 +- return drmIoctl(fd, DRM_IOCTL_MODE_CURSOR, &arg); 1.425 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_CURSOR, &arg); 1.426 + } 1.427 + 1.428 + /* 1.429 +@@ -510,7 +516,7 @@ int drmModeAttachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_inf 1.430 + memcpy(&res.mode, mode_info, sizeof(struct drm_mode_modeinfo)); 1.431 + res.connector_id = connector_id; 1.432 + 1.433 +- return drmIoctl(fd, DRM_IOCTL_MODE_ATTACHMODE, &res); 1.434 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_ATTACHMODE, &res); 1.435 + } 1.436 + 1.437 + int drmModeDetachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_info) 1.438 +@@ -520,7 +526,7 @@ int drmModeDetachMode(int fd, uint32_t connector_id, drmModeModeInfoPtr mode_inf 1.439 + memcpy(&res.mode, mode_info, sizeof(struct drm_mode_modeinfo)); 1.440 + res.connector_id = connector_id; 1.441 + 1.442 +- return drmIoctl(fd, DRM_IOCTL_MODE_DETACHMODE, &res); 1.443 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_DETACHMODE, &res); 1.444 + } 1.445 + 1.446 + 1.447 +@@ -637,16 +643,12 @@ int drmModeConnectorSetProperty(int fd, uint32_t connector_id, uint32_t property 1.448 + uint64_t value) 1.449 + { 1.450 + struct drm_mode_connector_set_property osp; 1.451 +- int ret; 1.452 + 1.453 + osp.connector_id = connector_id; 1.454 + osp.prop_id = property_id; 1.455 + osp.value = value; 1.456 + 1.457 +- if ((ret = drmIoctl(fd, DRM_IOCTL_MODE_SETPROPERTY, &osp))) 1.458 +- return ret; 1.459 +- 1.460 +- return 0; 1.461 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETPROPERTY, &osp); 1.462 + } 1.463 + 1.464 + /* 1.465 +@@ -715,7 +717,6 @@ int drmCheckModesettingSupported(const char *busid) 1.466 + int drmModeCrtcGetGamma(int fd, uint32_t crtc_id, uint32_t size, 1.467 + uint16_t *red, uint16_t *green, uint16_t *blue) 1.468 + { 1.469 +- int ret; 1.470 + struct drm_mode_crtc_lut l; 1.471 + 1.472 + l.crtc_id = crtc_id; 1.473 +@@ -724,16 +725,12 @@ int drmModeCrtcGetGamma(int fd, uint32_t crtc_id, uint32_t size, 1.474 + l.green = VOID2U64(green); 1.475 + l.blue = VOID2U64(blue); 1.476 + 1.477 +- if ((ret = drmIoctl(fd, DRM_IOCTL_MODE_GETGAMMA, &l))) 1.478 +- return ret; 1.479 +- 1.480 +- return 0; 1.481 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_GETGAMMA, &l); 1.482 + } 1.483 + 1.484 + int drmModeCrtcSetGamma(int fd, uint32_t crtc_id, uint32_t size, 1.485 + uint16_t *red, uint16_t *green, uint16_t *blue) 1.486 + { 1.487 +- int ret; 1.488 + struct drm_mode_crtc_lut l; 1.489 + 1.490 + l.crtc_id = crtc_id; 1.491 +@@ -742,10 +739,7 @@ int drmModeCrtcSetGamma(int fd, uint32_t crtc_id, uint32_t size, 1.492 + l.green = VOID2U64(green); 1.493 + l.blue = VOID2U64(blue); 1.494 + 1.495 +- if ((ret = drmIoctl(fd, DRM_IOCTL_MODE_SETGAMMA, &l))) 1.496 +- return ret; 1.497 +- 1.498 +- return 0; 1.499 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_SETGAMMA, &l); 1.500 + } 1.501 + 1.502 + int drmHandleEvent(int fd, drmEventContextPtr evctx) 1.503 +@@ -810,5 +804,5 @@ int drmModePageFlip(int fd, uint32_t crtc_id, uint32_t fb_id, 1.504 + flip.flags = flags; 1.505 + flip.reserved = 0; 1.506 + 1.507 +- return drmIoctl(fd, DRM_IOCTL_MODE_PAGE_FLIP, &flip); 1.508 ++ return DRM_IOCTL(fd, DRM_IOCTL_MODE_PAGE_FLIP, &flip); 1.509 + }